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Diploma in Information Technology (DIT) Calendar view

DCS1231 COMPUTER ORGANIZATION & ARCHITECTURE


Class
Azniah Zainal Abidin
Enrollment for this class is currently closed.

Lessons

Here is the class outline:

DCS1231 COA - Section 2

The course emphasizes computer architecture, including the structure and functions of the computer system. Other topics included are top-level view of a computer system that consists of a processor, bus interconnections and PCI. This course also introduces students the topics on internal, external memories, cache memory, hard disk functions and architecture, computer arithmetic, instruction sets, pipelining, CPU structure and function.

LESSON 1: INTRODUCTION TO COMPUTER ARCHITECTURE

1.1 Organization and architecture 1.2 Structure and function 1.3 Embedded system 1.4 Brief history of computer

Notes : Chapter 1 - Computer Architecture

LESSON 2: TOP LEVEL VIEW OF COMPUTER SYSTEM

2.1 Computer component 2.2 Types of processor 2.3 Bus interconnections 2.4 PCI

Chap 2 extra notes

LESSON 3 : MEMORY

3.1 Memory Characteristic 3.2 Internal memory 3.3 Secondary Storage

Ch 3

LESSON 4: : HARD DISK FUNCTIONS & ARCHITECTURE

4.1 Hard disk basic 4.2 Structure of hard disk 4.3 Writing and reading the data 4.4 Hard disk performance 4.5 Various types of hard disk 4.6 Factors affecting hard disk performance

Hard Disk

LESSON 5: CACHE MEMORY

5.1 Cache memory principles 5.2 Cache / main memory structure 5.3 Cache read operations 5.4 Elements of cache design

Cache

LESSON 6: COMPUTER ARITHMETIC

6.1 Integer representation (positive integer) 6.2 Integer representation (negative integer) 6.3 Integer arithmetic 6.4 Floating point representation

Computer Arithmetic

LESSON 7: INSTRUCTION SET

7.1 Machine instruction characteristics 7.2 Types of operands 7.3 Addressing mode

Chap 7 Slides

LESSON 8: CPU STRUCTURE & FUNCTIONS

8.1 Processor organization 8.2 Register organization 8.3 Instruction cycles

Slides ch 8

LESSON 9: PIPELINING

9.1 Pipeline operation 9.2 Cycle time of pipeline processor 9.3 Pipeline latency 9.4 Instruction hazard

Slides Ch 9
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